The Boolean expression can be extended to include multiple inputs to obtain a logic NAND operation. Similarly, the truth table of a three-input NAND logic gate is as follow: The truth table of a two-input NAND logic gate is shown below: An inversion bubble at the output denotes the inversion of the multiplication. The representation of a NAND logic by a symbol is shown in the following figure. Turning any of the inputs to logic “LOW” will drive the relative transistor to the “OFF” state and pulls the output (Q) high to VCC. When both inputs “A” and “B” are “HIGH” then both transistors are in saturated “ON” states and a state “LOW” appears at the output (Q). Figure 2: The Resistor-Transistor Logic NAND Gate In the following figure, a basic two-input NAND gate constructed using Resistor-Transistor Logic (RTL) is shown. The logic NAND gate is also referred to as Sheffer Stroke Function and is expressed by a vertical bar or arrow between the inputs. The dot (.) represents a logical multiplication whereas an overline represents a complement (NOT) of inputs. The logic NAND gate Boolean expression is denoted by a dot (.) placed between inputs and an overline. The logic NAND gate can be expressed through logic or Boolean expression of Logical Addition with its inputs inverted. Contrary to this, the logic NAND gate outputs logic “LOW” when all of its inputs are at logic level “HIGH” and it will output a logic “HIGH” when any of its inputs goes to the “LOW” state. The logic AND gate output logic “HIGH” when all of its inputs are at logic level “HIGH”.
It is a reverse or complement of a AND gate discussed previously. The NAND gate is a logic AND gate with an inverted output.
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